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Intel(R) Xeon(R) CPU E5-2695 v3

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fzs600:
 :kookoo:

J'ai une petite question de néophyte.
J'ai actuellement une config avec deux Xeon E5-2695 v3 (14 core/28 thread)

J'ai la possibilité d'acheté un seul Xeon E5-2699v3 (18 core/36 thread).

Est-ce possible de mixer un seul Xeon E5-2695 v3 et avec le Xeon E5-2699v3 ?

Merci.

 :jap:




Oncle Bob:
Il est apparemment possible de mixer 2 Xeons différents sous certaines conditions très restrictives. => https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-1.pdf#_OPENTOPIC_TOC_PROCESSING_d116e6281 (page 28)


--- Citer ---Mixing Processors

Intel supports and validates two configurations only in which all processors operate with the same Intel® QuickPath Interconnect frequency, core frequency, power segment, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel.
Combining processors from different power segments is also not supported.

Note: 
All processors within a system must run at a common maximum non-Turbo ratio. The system BIOS may be required to program the FLEX_RATIO register if mixed frequency processors are populated.
Not all operating systems can support dual processors with mixed frequencies. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, provided there is no more than one stepping delta between the processors,
for example, S and S+1.
S and S+1 is defined as mixing of two CPU steppings in the same platform where one CPU is S (stepping) = CPUID.(EAX=01h):EAX[3:0], and the other is S+1 = CPUID.
(EAX=01h):EAX[3:0]+1. The stepping ID is found in EAX[3:0] after executing the CPUID instruction with Function 01h. Details regarding the CPUID instruction are provided in the Intel® 64 and  IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M.
--- Fin de citation ---


Ici les caches L2 et L3 sont de tailles différentes (même si même quantité par cœur), donc ça me semble compromis (bien que ça ne soit pas hyper clair si on parle du cache total ou du cache/core).

fzs600:
J'ai relu plusieurs fois et même si je n'y comprend pas grand chose malgré tout, je n'est pas l'impression que cela soit possible.  :jap:

toTOW:
A mon avis, non ...

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